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design.v
testbench.sv
testbench.sv
1`include "uvm_macros.svh"
2import uvm_pkg::*;
3
4// ============================================
5// 8-bit Adder UVM Testbench - UVMHub Demo
6// ============================================
7
8// Transaction: defines stimulus data
9class adder_transaction extends uvm_sequence_item;
10 `uvm_object_utils(adder_transaction)
11
12 rand bit [7:0] operand_a;
13 rand bit [7:0] operand_b;
14 bit [8:0] result;
15
16 function new(string name = "tx");
17 super.new(name);
18 endfunction
19endclass
20
21// Driver: sends transactions to DUT
22class adder_driver extends uvm_driver #(adder_transaction);
23 `uvm_component_utils(adder_driver)
24
25 virtual adder_if vif;
26
27 task run_phase(uvm_phase phase);
28 adder_transaction tx;
29 forever begin
30 seq_item_port.get_next_item(tx);
31 @(posedge vif.clk);
32 vif.operand_a <= tx.operand_a;
33 vif.operand_b <= tx.operand_b;
34 vif.valid_in <= 1'b1;
35 `uvm_info("DRIVER", "Driving tx", UVM_MEDIUM)
36 seq_item_port.item_done();
37 end
38 endtask
39endclass
40
41// Monitor: observes DUT outputs
42class adder_monitor extends uvm_monitor;
43 `uvm_component_utils(adder_monitor)
44
45 virtual adder_if vif;
46 uvm_analysis_port #(adder_transaction) ap;
47
48 task run_phase(uvm_phase phase);
49 adder_transaction tx;
50 forever begin
51 @(posedge vif.valid_out);
52 tx = adder_transaction::type_id::create("tx");
53 tx.result = vif.result;
54 ap.write(tx);
55 `uvm_info("MONITOR", "Captured result", UVM_HIGH)
56 end
57 endtask
58endclass
59
60// Scoreboard: checks expected vs actual
61class adder_scoreboard extends uvm_scoreboard;
62 `uvm_component_utils(adder_scoreboard)
63
64 uvm_analysis_imp #(adder_transaction, adder_scoreboard) imp;
65 int pass_count = 0;
66 int fail_count = 0;
67
68 function void write(adder_transaction tx);
69 if (tx.result == tx.operand_a + tx.operand_b) begin
70 pass_count++;
71 `uvm_info("SB", "PASS", UVM_MEDIUM)
72 end else begin
73 fail_count++;
74 `uvm_error("SB", "FAIL")
75 end
76 endfunction
77endclass
Console Output
Lint
========================================

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The Verification Learning Challenge

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The Problem

Learning UVM traditionally takes 6+ months

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The Problem

Limited hands-on practice opportunities

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Difficult to debug complex verification issues

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The Problem

No standardized way to prove your skills

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Industry-recognized certifications that boost your career prospects

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Can I use UVMHub with my existing verification tools?

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Our certifications validate mastery of industry-standard verification methodologies. Many learners include them in their LinkedIn profiles and share them with employers.

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